Job Details:

Job Description: 

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany.

As part of Intel's strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in High-Volume Manufacturing (HVM) at a 2-year cadence going forward.

Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This job requisition is to seek FEOL (Front-End-Of-Line) Process Integration Development engineering roles in FSM HVM Global Yield organization, reporting to FEOL Process Integration Engineering Development manager. Selected candidates will work with other members in FEOL integration, other teams in Global Yield org, fab module, yield, and TD team members to achieve yield ramp-up and process optimization in early production stage, supporting internal and external customers.

 

FEOL (Front-End-Of-Line) Integration Development engineers' responsibilities include (but not limited to):

• Performs feasibility studies and provides integrated process solutions to meet desired safety, quality, reliability and output requirements for ultimate transfer to high volume manufacturing.
• Selects and develops material and equipment for the process to meet quality, reliability, cost, yield, productivity and manufacturability requirements.
• Plans and conducts experiment to fully characterize the process throughout the development cycle and to improve performance for each specific product.
• Identifies integrated process solutions to resolve issues or specific requests from customers by partnering with innovators in product engineering and module engineering teams.
• Conducts new product qualification and technology transfers from fabrication operations. Leverages big data analysis to identify process design weaknesses and/or manufacturing tool issues and proposes corrective, data-based solutions.
• Collaborates and engages with development and material suppliers, and partners to develop processes and equipment needs to meet technology roadmaps
• Own engineering projects to execute HVM yield roadmap, device targeting and attain performance targets.
• Collaborate with Technology Development and Local Yield teams to import new technology to production fabs.
• Work with FEOL/BEOL Integration, Device, Defect Reduction and Yield Analysis team members to identify root cause of yield/performance issues and implement mitigation plan in defined timeline to meet committed production yield/performance targets and to support fast paced yield ramp-up in high-volume manufacturing phases.
• Own NPI (New Product Introduction) in production fabs and perform product-specific process optimizations to meet foundry customers specifications and requirements.
• Own engineering projects in partnership with Local Yield teams to improve product yield, quality, device performance and to reduce wafer cost.
• Engineering support for technical interactions with internal and external customers.

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.

See https://www.intel.com/content/www/us/en/jobs/benefits.html for more details.

#GrowWithIntel

Qualifications:

You must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. The experience listed below may be obtained through schoolwork, classes and project work, internships, military training, and/or work experience.

Minimum Qualifications:

• PhD degree in Electrical Engineering, Electrical and Electronics Engineering, Material Science, or Physics. Other STEM related degrees could be considered as well.
• Semiconductor and transistor device physics knowledge
• ·Semiconductor processing fundamentals (lithography, wet etch, dry etch, chemical and or mechanical polishing, etc.)

 

         Preferred Qualifications:

        6+ months of experience in one of the following:

• Advanced transistor device structures and architectures (FinFET or GAA (Gate-All-Around) including fabrication (e.g., lithography (including EUV), etch, film deposition, cleans, chemical-mechanical planarization, etc.) with in-depth knowledge of semiconductor device physics and process integration.
• Statistics Coursework, Statistical Process Control (SPC) or Design of Experiments (DOE) principles, and engineering analysis tools.
• Data analysis skills with demonstrated ability to construct clear data-based problem statements.
• Experience in project/program management.
• Demonstrate solid communication skills, ability to work with multi-functional and multi-cultural teams.

          

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.