Post Silicon Validation Engineer - Google
Sunnyvale, CA
About the Job
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience in bringing up ASICs, performing validation, characterizing performance, and debugging failures.
- Experience scripting in Python or equivalent programming language.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 2 years of experience with C++/Python software design principles.
- Experience with hardware description languages (e.g., System Verilog) and chip design flow.
- Experience building test automation tools and scripts.
- Experience in bringing up high-power ASICs.
- Passion for unusual computer architectures.
About the job
In this role, you will work on the test design, bring-up, characterization, debug, and long term reliability of ASIC power management features. You will develop and execute test plans for functional verification and characterization. You will work closely with design, implementation, design verification, software developers, and prototyping in the development phase of the ASIC life-cycle, ensuring proper features are in place for post-silicon validation and debug. You will collaborate with system software and software test infrastructure developers to ensure we have proper ASIC test coverage for an entire program.
You will help develop a common set of requirements, processes, and tests to ensure smooth and reliable performance of ASIC projects. You will be working throughout the entire project life-cycle, from early pre-silicon planning and test development, through end-of-life characterization and failure debug. By leveraging hardware knowledge, you will develop and operate software-based tests for full investigation of ASIC operation.
You will work closely with both hardware and software teams to validate designs, and identify design issues. By working closely with designers, you will gain insight into the requirements for full ASIC test coverage. You will help to create and drive testing of our integrated systems with a focus on ASIC functional test verification and characterization.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Develop detailed test plans based on design specifications and coordination with a cross-functional team (e.g., architecture, design, software, firmware).
- Implement test plans by developing software tests and flows for system validation and verification.
- Perform long-term system characterization and debug and help root-cause failures. Provide feedback to improve power management quality, performance and reliability through generations of designs.
- Collaborate closely with firmware and software engineers and define required changes in power management algorithms to increase reliability and sustainability of ASICs.
