Senior Staff ASIC Digital Design Engineer - GreenWave Radios™
San Jose, CA
About the Job
InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.
Based in San Diego, California, GreenWave Radios™ has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology.
Are you looking to grow your career at a company that 93% of our current staff approve of our leadership, values, and goals?
To learn more about GreenWave Radios™, visit the GreenWave™ certification profile at GreatPlacetoWork.com and our website at Home - GreenWave Radios.
As a Staff or Senior Staff Engineer, Digital Design, you will be collaborating with a team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. You will also support other discipline teams to bring the SoC device to successful mass production.
This position can be based in San Jose, CA.
Key Responsibilities
- Review and contribute to SoC system architecture and product specifications
- Technical leadership supporting team resource planning, project scheduling and tracking
- Perform all aspects of complex SoC design flow from micro-architecture definitions, CPU/bus/memory sub-system design, IP integration, and verification through physical implementation
- Work with IP/Design Verification/Firmware/Software System/Production teams to provide necessary support for timely closure of SoC design and implementation issues
Job Requirements
- MS/Ph.D. in EE or equivalent and 10 or more years of experience in SoC development and mass production
- Knowledge of ARM/RISC Architectures, Multi-core CPU operation and system memory partition/hierarchy
- Experience with AMBA AXI/AHB/APB Protocol bus architecture specification and implementation
- Thorough knowledge of Verilog/VHDL/System Verilog languages and front-end tools such as simulation, linting, clock-domain crossing checking, formal verification
- Proven knowledge of constraint definition, synthesis, static timing analysis and complete Front to Back SoC design/implementation flow
- Understanding of SCAN ATPG, BIST, DFT/DFM and fault coverage analysis
- Proven knowledge of System Verilog/UVM methodology and other advanced design verification techniques
- Proficiency of programming/scripting languages such as C/C++, Perl, Tcl, and Python
- Great collaborator and team player with effective communication/presentation skills and aggressive schedule/quality result driven mentality
Desirable Skills
- Experience with Cadence F2B design tools
- Experience with formal verification tools
- Able to work effectively with incomplete or changing requirements
- Strong knowledge of mixed-signal concepts
Compensation and Benefits:
At InnoPhase, our compensation package includes base pay and pre-IPO stock options. The base pay range for this role is between $140K-$225K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.
