Sr. Silicon Design Verification Engineer at AMD
San Jose, CA 95101
About the Job
WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world
Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded
Underpinning our mission is the AMD culture
We push the limits of innovation to solve the world’s most important challenges
We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_THE ROLE: AMD’s Adaptive and Embedded Computing Group (AECG) is seeking Senior Silicon Design Verification Engineer, who can provide technical leadership and contribution on Verification of Network-on-Chip (NoC) and high-speed Memory Controller IPs
The individual will help design, develop, and use simulation and/or formal based verification environments, at block and full-chip level, to prove the functional correctness of Network-on-Chip (NoC), System-level Quality of Service (QoS) and DDR, LPDDR, and HBM Memory Controller IP designs.THE PERSON:A Senior Design Engineer will be a dynamic, quality-conscious, attention oriented individual with significant experience in successfully verifying products with high quality
Your experience and expertise in developing advance SystemVerilog and UVM based testbench and Automation that can scale with Full-Chip will enable improved execution of AMD’s devices and productivity
Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.KEY RESPONSIBILITIES:Collaborate with Architecture, Design, and Software teams to prove that the system-level architecture requirements are met as part of Pre-Silicon Functional Verification.Work includes Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs.Create Testbench Architecure - PREFERRED EXPERIENCE:The ideal candidate is one who has a proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS requirements. Requires strong understanding of AXI protocol, NoC architecture, DRAM memory controllers, especially DDR4/5, LPDDR4/5, and HBM2/2E/3.Requires experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify Full-Chip FPGA designs and memory controller IPs.Requires strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.Requires a familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.Experience with FPGA programming and software is a plus.Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.Experience with gate-level simulation, power-aware verification, reset verification, contention checking is a plus.Experience with silicon debug at the tester and board level is a plus. ACADEMIC CREDENTIALS:Requires BS, MS , PhD in Electrical Engineering, Computer Engineering, or Computer Science.ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA#LI-DW1#LI-HYBRIDAt AMD, your base pay is one part of your total rewards package
Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position
You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive
Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan
You’ll also be eligible for competitive benefits described in more detailhere.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.Job type: FULL TIMECategories: Engineering
Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded
Underpinning our mission is the AMD culture
We push the limits of innovation to solve the world’s most important challenges
We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_THE ROLE: AMD’s Adaptive and Embedded Computing Group (AECG) is seeking Senior Silicon Design Verification Engineer, who can provide technical leadership and contribution on Verification of Network-on-Chip (NoC) and high-speed Memory Controller IPs
The individual will help design, develop, and use simulation and/or formal based verification environments, at block and full-chip level, to prove the functional correctness of Network-on-Chip (NoC), System-level Quality of Service (QoS) and DDR, LPDDR, and HBM Memory Controller IP designs.THE PERSON:A Senior Design Engineer will be a dynamic, quality-conscious, attention oriented individual with significant experience in successfully verifying products with high quality
Your experience and expertise in developing advance SystemVerilog and UVM based testbench and Automation that can scale with Full-Chip will enable improved execution of AMD’s devices and productivity
Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.KEY RESPONSIBILITIES:Collaborate with Architecture, Design, and Software teams to prove that the system-level architecture requirements are met as part of Pre-Silicon Functional Verification.Work includes Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs.Create Testbench Architecure - PREFERRED EXPERIENCE:The ideal candidate is one who has a proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS requirements. Requires strong understanding of AXI protocol, NoC architecture, DRAM memory controllers, especially DDR4/5, LPDDR4/5, and HBM2/2E/3.Requires experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify Full-Chip FPGA designs and memory controller IPs.Requires strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.Requires a familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.Experience with FPGA programming and software is a plus.Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.Experience with gate-level simulation, power-aware verification, reset verification, contention checking is a plus.Experience with silicon debug at the tester and board level is a plus. ACADEMIC CREDENTIALS:Requires BS, MS , PhD in Electrical Engineering, Computer Engineering, or Computer Science.ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA#LI-DW1#LI-HYBRIDAt AMD, your base pay is one part of your total rewards package
Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position
You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive
Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan
You’ll also be eligible for competitive benefits described in more detailhere.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.Job type: FULL TIMECategories: Engineering
