UPF & Power Intent Hardware Engineer - HireTalent
Mountain View, CA 94043-0000
About the Job
Job Title: UPF & Power Intent Hardware Engineer
Job Location: Mountain View, CA
Job Duration: 3 Months on W2
Job Responsibilities:
Create & maintain UPF for complicated UPF blocks based on power intent specs and working with RTL engineers.
Guide RTL engineers on UPF creation for less complicated blocks.
Running of VCLP for Schip and SoC UPF creation.
Skills:
Creating UPF files at block, SoC levels & all levels in between.
Strong understanding of Power Intent requirements and specs.
Expert user of VCLP.
Power analysis & optimization skills are nice to have with PrimePower, PP-RTL/PowerArtist, Power Replay & Empower.
Typical Day in the Role:
" Purpose of the Team: The team works on silicon for AI; this team assists with pushing this from front end to back end. UPF, Powertent, and pushing the development of the AI chip through.
" Key Projects: This role will be responsible for when code is created; the candidate will create a UPF file and complete verification steps to ensure everything works correctly.
" Typical Task Breakdown and Operating Rhythm: The role will consist of 30% meetings/discussing issues that need resolving to drive fixes, 30% looking at dashboards and DCLP, 40% looking at UCF.
Top 3 Hard Skills Required + Years of Experience:
Minimum 3-5 years creating UPF files at block, SoC levels & all levels in between.
Minimum 3-5 years strong understanding of Power Intent requirements and specs.
Minimum 3-5 years as an expert user of VCLP.
Compelling Story & Candidate Value Proposition:
What makes this role interesting? - This role provides the opportunity to work on AI silicon which is a large scope of work and a lot of visibility to be driving an AI chip.
Summary:
UPF & Power Intent expert hardware engineer that has a proven record on power intent specs, UPF creation & verification.
Job Location: Mountain View, CA
Job Duration: 3 Months on W2
Job Responsibilities:
Create & maintain UPF for complicated UPF blocks based on power intent specs and working with RTL engineers.
Guide RTL engineers on UPF creation for less complicated blocks.
Running of VCLP for Schip and SoC UPF creation.
Skills:
Creating UPF files at block, SoC levels & all levels in between.
Strong understanding of Power Intent requirements and specs.
Expert user of VCLP.
Power analysis & optimization skills are nice to have with PrimePower, PP-RTL/PowerArtist, Power Replay & Empower.
Typical Day in the Role:
" Purpose of the Team: The team works on silicon for AI; this team assists with pushing this from front end to back end. UPF, Powertent, and pushing the development of the AI chip through.
" Key Projects: This role will be responsible for when code is created; the candidate will create a UPF file and complete verification steps to ensure everything works correctly.
" Typical Task Breakdown and Operating Rhythm: The role will consist of 30% meetings/discussing issues that need resolving to drive fixes, 30% looking at dashboards and DCLP, 40% looking at UCF.
Top 3 Hard Skills Required + Years of Experience:
Minimum 3-5 years creating UPF files at block, SoC levels & all levels in between.
Minimum 3-5 years strong understanding of Power Intent requirements and specs.
Minimum 3-5 years as an expert user of VCLP.
Compelling Story & Candidate Value Proposition:
What makes this role interesting? - This role provides the opportunity to work on AI silicon which is a large scope of work and a lot of visibility to be driving an AI chip.
Summary:
UPF & Power Intent expert hardware engineer that has a proven record on power intent specs, UPF creation & verification.
Source : HireTalent