Analog Layout Engineer - Meta

Summary:

Join Meta's Wearable Silicon AMS team as an Analog Layout Engineer and play a key role in developing cutting-edge AMS IP's that enable the next generation of virtual and augmented reality systems. As an Analog IC Layout Engineer, you will work with a world-class group of engineers creating high performance and area/power efficient custom layouts in advanced CMOS process nodes for our next generation AR/VR products. You will work closely with circuit designers and the physical design team to define the IC floor-plan, chip partitioning and power distribution.

Required Skills:

Analog Layout Engineer Responsibilities:

1. Design and optimize complex layouts for mixed signal and analog circuits in deep sub-micron CMOS technologies

2. Collaborate with circuit designers to floor plan and complete layouts, ensuring seamless integration and optimal performance

3. Run physical design/reliability verification, debug and fix violations, ensuring the highest quality and reliability of our AMS IP's

4. Review and analyze layouts with circuit designers, providing expert feedback and guidance to ensure optimal design

5. Contribute to layout integration and final verification for tape out, ensuring a smooth and successful project delivery

Minimum Qualifications:

Minimum Qualifications:

6. Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.

7. Bachelor's degree in Electrical Engineering, or relevant technical field, or equivalent practical experience

8. 3+ years of experience as an IC Layout Designer with analog/mixed signal layout experience

9. Proven experience with layout techniques for device matching, noise isolation, electro-migration, power distribution, latch-up and ESD circuits using state of the art nanometer process technologies

10. Proficiency with Cadence Virtuoso XL layout tool and Mentor Calibre physical design verification tools (DRC, LVS, ERC) or equivalent

11. Experience debugging and resolve LVS/DRC/ERC errors independently

Preferred Qualifications:

Preferred Qualifications:

12. Exposure to FinFET process technology and its constraints for analog layout techniques and qualities

13. Familiarity with Cadence Virtuoso advanced features, such as schematic and constraint driven layout, auto routing

14. Experience with Place and Route tools and scripting languages (perl, TCL, Python, or Cadence Skill)

15. Experience with memory layout

Public Compensation:

$95,400/year to $166,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.