ASIC Design Verification Engineer, Google Cloud - Google
Sunnyvale, TX 75182
About the Job
Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.Experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.Experience with SystemVerilog (i.e
SystemVerilog Assertions or functional coverage).Preferred qualifications:Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.6 years of experience in design verification.Experience with one or more of the following: networking, switching, congestion control protocols, PCIe, TCP/IP, RDMA, NVMe, or ARM interconnect protocols.Experience in Power aware verification, Gate level simulations, and Post silicon bring-up.Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for Application-Specific Integrated Circuits (ASICs).Familiarity with ASIC standard interfaces and memory system architecture
About the job As a ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers
You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification, and silicon bringup
You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running
From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible
We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them
We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits
Our salary ranges are determined by role, level, and location
The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations
Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training
Your recruiter can share more about the specific salary range for your preferred location during the hiring process
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits
Learn more about benefits at Google
Responsibilities Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).Identify and write all types of coverage measures for stimulus and corner-cases.Debug tests with design engineers to deliver correct design blocks.Close coverage measures to identify verification holes and to show progress towards tape-out.
SystemVerilog Assertions or functional coverage).Preferred qualifications:Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.6 years of experience in design verification.Experience with one or more of the following: networking, switching, congestion control protocols, PCIe, TCP/IP, RDMA, NVMe, or ARM interconnect protocols.Experience in Power aware verification, Gate level simulations, and Post silicon bring-up.Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for Application-Specific Integrated Circuits (ASICs).Familiarity with ASIC standard interfaces and memory system architecture
About the job As a ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers
You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification, and silicon bringup
You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running
From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible
We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them
We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits
Our salary ranges are determined by role, level, and location
The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations
Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training
Your recruiter can share more about the specific salary range for your preferred location during the hiring process
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits
Learn more about benefits at Google
Responsibilities Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).Identify and write all types of coverage measures for stimulus and corner-cases.Debug tests with design engineers to deliver correct design blocks.Close coverage measures to identify verification holes and to show progress towards tape-out.
Source : Google