ASIC STA Engineer - Cisco
San Jose, CA
About the Job
Who We Are
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed.
Who you’ll work with
You will collaborate with ASIC Front and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips, working closely with the timing lead on backend timing signoff, including CDC checks, static timing verification, and silicon debugging.
What you’ll do
You will be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. Additionally, you’ll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.
Who you are
You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing analysis concepts, such as setup/hold times, noise, and crosstalk. With expertise in industry-standard STA tools and proficiency in scripting for automation, you excel at identifying and resolving timing issues across all levels of design. You collaborate effectively with cross-functional teams, communicate complex timing data clearly, and are always focused on driving designs to closure.
Minimum Qualifications
* Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 7+ years of related work experience.
* Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
* Timing closure with various timing ECO including transition, setup, hold, noise, xtalk, and power recovery.
* Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates
* Scripting: TCL, Perl, or Python.
Preferred Qualifications
* Master’s Degree in electrical or computer engineering (or other equivalent field) with 5+ years of related work experience.
* Synthesis Tools: Synopsys DC/DCG/FC.
* Formal Verification: Synopsys Formality and Cadence LEC.
* Parasitic Extraction: Synopsys Star-RCXT, Cadence Quantus.
* Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus.
Why Cisco
#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company.
We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it).
Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.
Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!
#WeAreCisco
Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.
Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed.
Who you’ll work with
You will collaborate with ASIC Front and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips, working closely with the timing lead on backend timing signoff, including CDC checks, static timing verification, and silicon debugging.
What you’ll do
You will be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. Additionally, you’ll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.
Who you are
You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing analysis concepts, such as setup/hold times, noise, and crosstalk. With expertise in industry-standard STA tools and proficiency in scripting for automation, you excel at identifying and resolving timing issues across all levels of design. You collaborate effectively with cross-functional teams, communicate complex timing data clearly, and are always focused on driving designs to closure.
Minimum Qualifications
* Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 7+ years of related work experience.
* Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
* Timing closure with various timing ECO including transition, setup, hold, noise, xtalk, and power recovery.
* Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates
* Scripting: TCL, Perl, or Python.
Preferred Qualifications
* Master’s Degree in electrical or computer engineering (or other equivalent field) with 5+ years of related work experience.
* Synthesis Tools: Synopsys DC/DCG/FC.
* Formal Verification: Synopsys Formality and Cadence LEC.
* Parasitic Extraction: Synopsys Star-RCXT, Cadence Quantus.
* Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus.
Why Cisco
#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company.
We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it).
Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.
Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!
#WeAreCisco
Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.
Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.
Source : Cisco
