Desgn Verificatn Engineer at Astera Labs, Inc.
Santa Clara , CA 95054
About the Job
ENGINEER
Astera Labs, Inc. (Santa Clara, CA) Multiple FT positions. Desgn Veri-ficatn Engr: define comprhensv dsgn verificatn + emu-latn or prototyp methodlgy 4 com-plx SoC; req Mastr or equiv + spec skills.$151091-160k. Semiconductor Packagng Engr: define pack-ge of POR + impl. /simul./correl. Ethernet, PCIe+ DDR interfaces; req Master or equiv + spec skills. $156624-$165k. Visit www. asteralabs.com or send resumes to careers@astera labs.com. Principals only. EOE.
Astera Labs, Inc. (Santa Clara, CA) Multiple FT positions. Desgn Veri-ficatn Engr: define comprhensv dsgn verificatn + emu-latn or prototyp methodlgy 4 com-plx SoC; req Mastr or equiv + spec skills.$151091-160k. Semiconductor Packagng Engr: define pack-ge of POR + impl. /simul./correl. Ethernet, PCIe+ DDR interfaces; req Master or equiv + spec skills. $156624-$165k. Visit www. asteralabs.com or send resumes to careers@astera labs.com. Principals only. EOE.
