Design Verification Engineer - Advanced Micro Devices, Inc

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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TITLE : Design Verification Engineer

THE ROLE :

In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. You will be leading IP functional verification tasks. This team also is responsible for the Design and Verification of several critical as well as the integration to other subsystems and SoC. The Design and Design Verification groups within this team are also responsible for developing a balanced architecture between power consumption and performance, delivering high complexity RTL code and creating sophisticated testbenches using groundbreaking verification techniques.

THE PERSON :

• Strong analytical and problem solving skills with pronounced attention to detail

• Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality

• Someone who enjoys debugging

• Person who can handle stressful environments while coming up with new insights

RESPONSIBILITIES:

Collaborate with design team to understand and define verification requirements for high-speed, low power digital circuit designs from definition to implementation. Own or be involved in all aspects of the functional verification from initial test planning, test creation and debug. to coverage and sign-off closure, while providing technical leadership to the team.

Own verification of high speed, low power digital designs at IP and System level using both coverage driven constraint random and directed testing techniques as well as formal verification. Implement test benches and components such as test and sequence libraries, monitors, models and BFMs by applying objected oriented programming verification techniques following UVM methodology.

PREFERRED SKILL SETS :

• Advanced knowledge of ASIC Design flow and state of the art verification flow

• Proficient with Verilog, System Verilog and UVM

• Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus

• Test bench creation and Test environments

EDUCATION :

• Major in EE, CS or related, Master Degree 

LOCATION:

Santa Clara, CA

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.