Design Verification Engineer - Tanisha Systems

6+ years of hands-on DV experience in object oriented programming in SystemVerilog/UVM.

Must be able to own and drive the verification of a block / subsystem or a SOC.

Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.

Experience in Tesplan and Testbench development,

Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.

Should be good with debugging and exposed to all aspects of verification flow including Gatesims

Must have extensive experience in verification of one or more of the following:

oAXI, ACE or CHI

oARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages

Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.

Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase.

Experience in SVA and formal verification is desirable (not a must)

Must have Python coding experience.