Design Verification Engineers - SystemVerilog - USA - Steinman Recruiting Associates

We seek engineering talent with proven accomplishments in either complex digital or mixed signal design verification. You will create design verification solutions in a SystemVerilog environment. Design test bed solutions from scratch. UVM libraries. Test bench code. Our clients derive significant revenue developing the latest in the power, wireless, mobile, digital health, automotive, AI, AR, Deep and Machine Learning. Next generation IC designs (Mixed Signal, Digital, Analog, ASIC, SoC, CPU, GPU, FPGA).

* We also have additional opportunities with awesome clients in Dallas, Phoenix, San Fran Bay - Valley, and Raleigh Durham involve Digital Design, Analog - Mixed Signal Design, System Architecture, Product Test, Product Engineering, Silicon Project Management, Applications and Technical Marketing *

Title: Design Verification Engineer (mid –> senior –> lead levels)

Locations: Phoenix, Austin, RTP, San Jose. Hybrid onsite 2-3 days weekly. Relocation packages are comprehensive.

Compensation: Depending on skill - experience level, base salaries $130,000 - $210,000. Lucrative bonuses. RSUs. Stellar benefit packages.

Technical proficiency in several of the following:

- Test plans, testbenches, and verification methodologies, developing test benches from scratch

- Directed/constraint-random test generation, gate-simulations

- Formal verification methodology, i.e. OVM, UVM, AVM

- Strong background in HDLs

- RTL design

- SystemVerilog

- Verilog AMS

- Signal Processing

- Behavioral Models

- Verilog Assertions

- HW Acceleration

- HW Emulation

** Current H1B visa holders or TN eligible professionals are encouraged to apply **