Digital Design Engineer - Meta
About the Job
As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design skills to implement and contribute to development and optimization of state of the art vision and sensing algorithms. You will also support the Digital Silicon Architects developing and implementing the next generation custom and semi-custom mixed signal ICs to drive our industry leading virtual and augmented reality systems.
RESPONSIBILITIES
Digital Design Engineer Responsibilities:
MINIMUM QUALIFICATIONS
Minimum Qualifications:
PREFERRED QUALIFICATIONS
Preferred Qualifications:
RESPONSIBILITIES
Digital Design Engineer Responsibilities:
- Responsible for top-level or block level µArchitecture definition and design of Computer Vision/Image Sensing IP.
- Contribute to chip-level integration, verification plan development and verification.
- Define timing constraints, run synthesis and static timing analysis.
- Support the test program development, chip validation and chip life until production maturity.
- Work with FPGA/Emulation engineers to perform early prototyping.
- Support hand-off and integration of blocks into larger SOC environments.
- Assist with performance/power analysis of the design and help meet the power requirements.
MINIMUM QUALIFICATIONS
Minimum Qualifications:
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 7+ years of experience as a Digital Design Engineer
- Experience with top level integration using automation tools.
- Experience in RTL coding, synthesis and/or SoC Integration.
- Experience in digital design µArchitecture.
- Experience with at least 1 procedural programming language (C, C++, Python etc.).
PREFERRED QUALIFICATIONS
Preferred Qualifications:
- Experience with Computer Vision or Image Signal Processing accelerators.
- Experience with HLS flow for data path implementation.
- SystemVerilog OVM/UVM experience.
- Experience in SoC integration and ASIC architecture.
- Experience with low power design and optimization, including UPF flow.
- Experience with design synthesis and timing optimization.
- Master's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
Source : Meta
