Hardware Engineering and R&D - Hardware Design Engineer 5 Hardware Design Engineer 5 - HireTalent
Mountain View, CA 94043-0000
About the Job
Job Title: Hardware Design Engineer 5
Location: Mountain View, CA
Duration: 4 months on W2 (Chance for 18 months)
Typical Day in the Role
" Purpose of the Team: The purpose of this team is SVC Validation team. After Silicon comes back the team debugs the devices and runs tests to ensure the silicon
" Key projects: This role will contribute to Evergreen Projects at the Sky level. These are exploratory projects and don't entail hard processes in place but require engineers to work beyond the team guidelines and provide new processes and implementation.
" Typical task breakdown and operating rhythm: The role will consist of Develop/Augment post-Si test generators.
Candidate Requirements
" Years of Experience Required: 10 overall years of experience in the field.
" Degrees or certifications required: Bachelor's degree in engineering required.
" Disqualifiers: Job hopping and industry mismatches
" Best vs. Average: The ideal resume would contain silicon experience and have worked in the lab. If a candidate has also worked at MSFT in SVC this would be highly preferred as well.
" Performance Indicators: Performance will be assessed based on meeting deadlines and ability to work independently.
Hard Skills Assessments
" Expected Dates that Hard Skills Assessments will be scheduled: As soon as possible.
" Hard Skills Assessment Process: The assessment process will include 1-3 rounds of interviews.
Required Candidate Preparation: Candidate needs to be able to prove they have experience with the hard skill requirements.
Skills:
Deep understanding of pre-Si DV test generation techniques and applicability to post si-test generation
Experience with constrained random test generators/techniques
Understanding of pre and post Si coverage
Experience with pre-Silicon Simulation and Emulation platforms
Python, C/C++, experience with base metal and Linux OS, embedded SW deve3lopment, Git/Perforce
Prior Tools and Methodology development experience
Strong SW skills
Education/Experience:
" Bachelor's degree in engineering required.
" 10+ years experience required.
Top 3 Hard Skills Required + Years of Experience
1. Minimum 10 years experience with Deep understanding of pre-Si DV test generation techniques and applicability to post si-test generation
2. Minimum 10 years experience with constrained random test generators/techniques
3.Minimum 10 years experience with Python, C/C++, experience with base metal and Linux OS, embedded SW development, Git/Perforce
Location: Mountain View, CA
Duration: 4 months on W2 (Chance for 18 months)
Typical Day in the Role
" Purpose of the Team: The purpose of this team is SVC Validation team. After Silicon comes back the team debugs the devices and runs tests to ensure the silicon
" Key projects: This role will contribute to Evergreen Projects at the Sky level. These are exploratory projects and don't entail hard processes in place but require engineers to work beyond the team guidelines and provide new processes and implementation.
" Typical task breakdown and operating rhythm: The role will consist of Develop/Augment post-Si test generators.
Candidate Requirements
" Years of Experience Required: 10 overall years of experience in the field.
" Degrees or certifications required: Bachelor's degree in engineering required.
" Disqualifiers: Job hopping and industry mismatches
" Best vs. Average: The ideal resume would contain silicon experience and have worked in the lab. If a candidate has also worked at MSFT in SVC this would be highly preferred as well.
" Performance Indicators: Performance will be assessed based on meeting deadlines and ability to work independently.
Hard Skills Assessments
" Expected Dates that Hard Skills Assessments will be scheduled: As soon as possible.
" Hard Skills Assessment Process: The assessment process will include 1-3 rounds of interviews.
Required Candidate Preparation: Candidate needs to be able to prove they have experience with the hard skill requirements.
Skills:
Deep understanding of pre-Si DV test generation techniques and applicability to post si-test generation
Experience with constrained random test generators/techniques
Understanding of pre and post Si coverage
Experience with pre-Silicon Simulation and Emulation platforms
Python, C/C++, experience with base metal and Linux OS, embedded SW deve3lopment, Git/Perforce
Prior Tools and Methodology development experience
Strong SW skills
Education/Experience:
" Bachelor's degree in engineering required.
" 10+ years experience required.
Top 3 Hard Skills Required + Years of Experience
1. Minimum 10 years experience with Deep understanding of pre-Si DV test generation techniques and applicability to post si-test generation
2. Minimum 10 years experience with constrained random test generators/techniques
3.Minimum 10 years experience with Python, C/C++, experience with base metal and Linux OS, embedded SW development, Git/Perforce
Source : HireTalent
