Hardware Engineering - Silicon DD Engineer III Silicon DD Engineer III - PRI Global
Remote Location, CA 94025
About the Job
Job Description: Position Title: Silicon DD Engineer
Start Date: October 7, 2024
Length of Contract: 12 months
Location: US CA Remote
Is this role remote?: Yes (open to US-wide)
Max Bill Rate:
Reason for Opening: Increased volumes
Role Mandate:
The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on uarchitecture development and perform RTL coding on the next version of our IP. This individual will have the opportunity to work on block design implementation for an IP that is going into future AR products.
Candidate Value Proposition:
The ideal candidate will collaborate with a team of designers to work on graphics IP development.
Role Responsibilities (including, but not limited to):
" Own ASIC IP RTL implementation for IP blocks.
" Ensure RTL written meets quality checks like Lint/CDC/RDC.
" Collaborate closely with design team members, technical leads and the architecture team to ensure the block meets the power and performance requirements.
" Collaborate closely with the verification team to develop test plans and review test coverage.
" Perform IP integration
" Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
" Work with FPGA engineers to perform early prototyping
" Support hand-off and integration of blocks into larger SOC environments
" Assist with Algorithm analysis.
Performance Measurement:
Performance is measured based on meeting deadlines by delivering on time while meeting code quality metrics and DV quality metrics.
Must Have Skills:
" 4+ years of experience as a Digital Design Engineer.
" Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC (Per CWAM, anything beyond would be a challenge)
" Experience having worked on a design from scratch code from the ground up (outline / provide project work, if available)
" Experience in RTL coding and coding for low power in ASICs
" Experience in digital design Architecture
" Strong experience with Verilog and SystemVerilog coding
" Perl, Tcl and Python (or similar) scripting experience
Nice-to-Have Skills:
" MSEE/CS or equivalent experience
" Experience developing IP for Graphics Processing Unit (GPU), CPU, Compression, or Video ASICs experience working on coding for these industries (typically aligns with what this team is doing)
" Recent track record of projects where individual coded from ground up that were successfully taped out.
" Former Meta experience
Soft Skills:
" Strong verbal and written communication skills
Educational Requirements:
" BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience
Skills Assessment:
" 2 Rounds, 45 mins 1 hour
" Coding exercises - fixed/floating point datapath design and ctrl path/FSM design in system Verilog
**Additional Note to the Recruiter Do Not Distribute**
" The team is looking for engineers to do the actual design, not maintenance
" Recent experience with RTL coding within the past 2-3 years (anything beyond would be a struggle)
" What are the top non-negotiable skill sets required for this role?
o Experience in RTL coding, synthesis and/or SoC Integration
o Experience in digital design Architecture
o Familiarity with Verilog, system Verilog coding
" Former AMD, NVIDIA, Apple, Qualcomm, Client, Microsoft (on Silicon side) candidates (nice-to-have)
Red Flags / Disqualifiers
" Lack of RTL coding
" Lots of job hopping / large unexplained gaps within resume
" Lighter side of industry experience
" Lots of short-term engagements
CWAM will reject candidates based on resume if:
- Lack of hands-on coping / IP block design and / or no recent design experience (recent within 2-3 years)
- Very rusty on RTL coding, most design work was 10 or so years back. Candidate also lacked experience in low power design. Basic coding issues in the design portion of the interview
- Candidate's design experience seemed to be limited to mostly FSM based designs (i.e. no caches, some limited fixed point math in filters). Candidate struggled a lot with two fairly basic coding questions.
- Experience seems to be RF related, not IP block design
- Looks like very limited RTL design experience mostly around DDR PHY design, not relevant to our designs
- No ASIC RTL design experience. Only design seems to be as a FW engineer targeting FPGA. GPU experience seems to be system verification/test infrastructure related, not design
- Limited block design experience, seems mostly integration related
- Design experience seems to be very simple blocks like performance monitors
- Experience is DV and silicon validation, not design
Notes on rejected candidates that previously had an interview:
- Lack of significant recent IP block design experience, design seems limited to PHY components
- While candidate had recent design experience on an HBM controller, the candidate's actual contribution was just a serializer/deserializer IP that was used. Overall candidate's actual design experience was very limited. Candidate's performance in the coding questions was below expectations.
- Seems to have experience more in sensor design, not IP block design
- Candidate has mostly PD experience, recent design experience is only about a year and a simple i2c design
- Candidate s experience is DFT/PD not IP block design
- Candidate s experience is all FPGA
- Design experience seems to be less on the IP side and more on the standard component side of things
- No IP development experience; seems like all experiences are related to low power/UPF flow and design quality check flows, like LEC, lint/cdc
- System Verilog experience is fairly limited and seems like mostly small designs
- Candidate s experience is limited to NAND controllers, do not see a lock of block design experience
- Work seems to be mostly integration work and small modifications to IP
- Most recent experience (~4 years) is in design verification and FPGA integration work. Design work prior to that seems to be very simple designs
- Experience is a bit confusing, not sure what is IP that they implemented vs. solutions they produced integrating various CPU/DSP cores. Experience is largely FPGA
- All experience is FPGA
- Candidate's design experience was really just a fairly simple block that would do in order processing of SSD data. Candidate performed below expectations in both easy coding questions.
- Block design experience is limited to simple PMU/I2C designs
- Candidate was upfront about the fact that the sole block that they worked on at Broadcom over the last 11 years was a fairly small design - effectively just a few FSMs talking to a serial interface. This lack of design experience was very apparent in TC's struggle with the first basic coding question.
Comments for Suppliers:
Start Date: October 7, 2024
Length of Contract: 12 months
Location: US CA Remote
Is this role remote?: Yes (open to US-wide)
Max Bill Rate:
Reason for Opening: Increased volumes
Role Mandate:
The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on uarchitecture development and perform RTL coding on the next version of our IP. This individual will have the opportunity to work on block design implementation for an IP that is going into future AR products.
Candidate Value Proposition:
The ideal candidate will collaborate with a team of designers to work on graphics IP development.
Role Responsibilities (including, but not limited to):
" Own ASIC IP RTL implementation for IP blocks.
" Ensure RTL written meets quality checks like Lint/CDC/RDC.
" Collaborate closely with design team members, technical leads and the architecture team to ensure the block meets the power and performance requirements.
" Collaborate closely with the verification team to develop test plans and review test coverage.
" Perform IP integration
" Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
" Work with FPGA engineers to perform early prototyping
" Support hand-off and integration of blocks into larger SOC environments
" Assist with Algorithm analysis.
Performance Measurement:
Performance is measured based on meeting deadlines by delivering on time while meeting code quality metrics and DV quality metrics.
Must Have Skills:
" 4+ years of experience as a Digital Design Engineer.
" Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC (Per CWAM, anything beyond would be a challenge)
" Experience having worked on a design from scratch code from the ground up (outline / provide project work, if available)
" Experience in RTL coding and coding for low power in ASICs
" Experience in digital design Architecture
" Strong experience with Verilog and SystemVerilog coding
" Perl, Tcl and Python (or similar) scripting experience
Nice-to-Have Skills:
" MSEE/CS or equivalent experience
" Experience developing IP for Graphics Processing Unit (GPU), CPU, Compression, or Video ASICs experience working on coding for these industries (typically aligns with what this team is doing)
" Recent track record of projects where individual coded from ground up that were successfully taped out.
" Former Meta experience
Soft Skills:
" Strong verbal and written communication skills
Educational Requirements:
" BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience
Skills Assessment:
" 2 Rounds, 45 mins 1 hour
" Coding exercises - fixed/floating point datapath design and ctrl path/FSM design in system Verilog
**Additional Note to the Recruiter Do Not Distribute**
" The team is looking for engineers to do the actual design, not maintenance
" Recent experience with RTL coding within the past 2-3 years (anything beyond would be a struggle)
" What are the top non-negotiable skill sets required for this role?
o Experience in RTL coding, synthesis and/or SoC Integration
o Experience in digital design Architecture
o Familiarity with Verilog, system Verilog coding
" Former AMD, NVIDIA, Apple, Qualcomm, Client, Microsoft (on Silicon side) candidates (nice-to-have)
Red Flags / Disqualifiers
" Lack of RTL coding
" Lots of job hopping / large unexplained gaps within resume
" Lighter side of industry experience
" Lots of short-term engagements
CWAM will reject candidates based on resume if:
- Lack of hands-on coping / IP block design and / or no recent design experience (recent within 2-3 years)
- Very rusty on RTL coding, most design work was 10 or so years back. Candidate also lacked experience in low power design. Basic coding issues in the design portion of the interview
- Candidate's design experience seemed to be limited to mostly FSM based designs (i.e. no caches, some limited fixed point math in filters). Candidate struggled a lot with two fairly basic coding questions.
- Experience seems to be RF related, not IP block design
- Looks like very limited RTL design experience mostly around DDR PHY design, not relevant to our designs
- No ASIC RTL design experience. Only design seems to be as a FW engineer targeting FPGA. GPU experience seems to be system verification/test infrastructure related, not design
- Limited block design experience, seems mostly integration related
- Design experience seems to be very simple blocks like performance monitors
- Experience is DV and silicon validation, not design
Notes on rejected candidates that previously had an interview:
- Lack of significant recent IP block design experience, design seems limited to PHY components
- While candidate had recent design experience on an HBM controller, the candidate's actual contribution was just a serializer/deserializer IP that was used. Overall candidate's actual design experience was very limited. Candidate's performance in the coding questions was below expectations.
- Seems to have experience more in sensor design, not IP block design
- Candidate has mostly PD experience, recent design experience is only about a year and a simple i2c design
- Candidate s experience is DFT/PD not IP block design
- Candidate s experience is all FPGA
- Design experience seems to be less on the IP side and more on the standard component side of things
- No IP development experience; seems like all experiences are related to low power/UPF flow and design quality check flows, like LEC, lint/cdc
- System Verilog experience is fairly limited and seems like mostly small designs
- Candidate s experience is limited to NAND controllers, do not see a lock of block design experience
- Work seems to be mostly integration work and small modifications to IP
- Most recent experience (~4 years) is in design verification and FPGA integration work. Design work prior to that seems to be very simple designs
- Experience is a bit confusing, not sure what is IP that they implemented vs. solutions they produced integrating various CPU/DSP cores. Experience is largely FPGA
- All experience is FPGA
- Candidate's design experience was really just a fairly simple block that would do in order processing of SSD data. Candidate performed below expectations in both easy coding questions.
- Block design experience is limited to simple PMU/I2C designs
- Candidate was upfront about the fact that the sole block that they worked on at Broadcom over the last 11 years was a fairly small design - effectively just a few FSMs talking to a serial interface. This lack of design experience was very apparent in TC's struggle with the first basic coding question.
Comments for Suppliers:
Source : PRI Global
