Physical Design Engineer, Static Timing Analysis at Google

Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.8 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).Experience with EDA tools (i.e. Primetime, Tempus, Timevision, STAR-RC) and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk.Preferred qualifications:12 years of experience in the domain of static timing analysis.Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.Experience in extraction of design parameters, QoR metrics, and analyzing data trends.Knowledge of semiconductor device physics and,Working knowledge of SPICE simulation and complex full-chip static timing topics, including complex clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.As a Physical Design Engineer on the chip implementation team, you will work on the physical implementation of ASICs using advanced technology nodes. You will work on constraint development and timing closure of large complex high performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. You will perform technical evaluations of vendors, tools, methodologies, and will provide recommendations. Additionally, you will work with architecture, logic design, and DFT teams to understand and implement their requirements.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Perform a dual role of static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.Own full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip timing analysis and timing ECO creation, and oversee final timing signoff for complex ASICs.Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.Perform technical evaluations of EDA tools and provide recommendations, documentation, and training.Debug flow issues reported by your wider team and work with EDA vendors to resolve them where necessary.