Physical Design Lead – Custom Silicon Management at Apple
Cupertino, CA 95014
About the Job
SummaryPosted: Role Number:200511382Are you a leader and want to apply your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule?
The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV
We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies
We are looking for a remarkable Physical Design Lead to work with a highly hardworking Custom Silicon team at Apple to design and develop innovative chips for the coolest products
This position focuses specifically on supporting Physical Design and related activities for the chips.DescriptionYou will have the opportunity to integrate and come-up with new insights, as well as work with vendors to promote efficiency in the Silicon community.
We value your technical understanding of physical design principles
You will be responsible for ensuring the high quality of the chips and is expected to:
•Audit vendor PD flows and methodologies for any holes and set up issues.
•Suggest improvements to their methodology to optimize it to obtain the best QoR for Apple chips.
•Work closely with the internal teams like systems and program management to ensure that the vendor PD implementation team is meeting the design goals.
•Work closely with specialists from other teams like the packaging, process etc
to resolve any issues in the project which are in an area closely related to PD.
•Conduct periodic design reviews - with deep technical dives - to make sure the project is tracking to the schedule and maintaining a high quality of work.
•Review all the final PD, STA, SI, Electrical analysis reports and sign-off on them for tapeout approval.
•Provide post tapeout support to work on ECOs and debug, if required.
•Adhere to a strict and consistent standard of operation across all vendors and projects.
•Maintain a professional relationship with the vendor and yet walk the fine line to maintain the customer-vendor distance.Key Qualifications10+ years of experience in Physical Design of SoCs.5+ years of experience in leading physical design teams.Proven track record of having taped out a number of complex chips - from gates to GDS.Good knowledge of digital design concepts.Working knowledge of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques.In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification.Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech.Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing.Hands-on experience in Power and Signal Integrity analysis.Ability to debug and fix LVS, DRC, Antenna, ERC issues.Familiarity with the best analog layout design practices for sensitive circuits like OpAmp, matching pair, etc.Mixed signal SoC tapeouts involving multiple instances of analog IPs.Low power / leakage management methodology and techniques.Extraction and characterization of IP elements.Education & ExperienceBS and 20 plus years of relevant industry experience (MSEE/PhD in Electrical Engineering Preferred)Additional Requirements25-30% Travel RequiredPay & BenefitsAt Apple, base pay is one part of our total compensation package and is determined within a range
This provides the opportunity to progress as you grow and develop within a role
The base pay range for this role is between $165,500 and $293,800, and your base pay will depend on your skills, qualifications, experience, and location.Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs
Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan
You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition
Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation
Learn more about Apple Benefits.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.Apple is an equal opportunity employer that is committed to inclusion and diversity
We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics
Learn more about your EEO rights as an applicant.
The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV
We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies
We are looking for a remarkable Physical Design Lead to work with a highly hardworking Custom Silicon team at Apple to design and develop innovative chips for the coolest products
This position focuses specifically on supporting Physical Design and related activities for the chips.DescriptionYou will have the opportunity to integrate and come-up with new insights, as well as work with vendors to promote efficiency in the Silicon community.
We value your technical understanding of physical design principles
You will be responsible for ensuring the high quality of the chips and is expected to:
•Audit vendor PD flows and methodologies for any holes and set up issues.
•Suggest improvements to their methodology to optimize it to obtain the best QoR for Apple chips.
•Work closely with the internal teams like systems and program management to ensure that the vendor PD implementation team is meeting the design goals.
•Work closely with specialists from other teams like the packaging, process etc
to resolve any issues in the project which are in an area closely related to PD.
•Conduct periodic design reviews - with deep technical dives - to make sure the project is tracking to the schedule and maintaining a high quality of work.
•Review all the final PD, STA, SI, Electrical analysis reports and sign-off on them for tapeout approval.
•Provide post tapeout support to work on ECOs and debug, if required.
•Adhere to a strict and consistent standard of operation across all vendors and projects.
•Maintain a professional relationship with the vendor and yet walk the fine line to maintain the customer-vendor distance.Key Qualifications10+ years of experience in Physical Design of SoCs.5+ years of experience in leading physical design teams.Proven track record of having taped out a number of complex chips - from gates to GDS.Good knowledge of digital design concepts.Working knowledge of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques.In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification.Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech.Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing.Hands-on experience in Power and Signal Integrity analysis.Ability to debug and fix LVS, DRC, Antenna, ERC issues.Familiarity with the best analog layout design practices for sensitive circuits like OpAmp, matching pair, etc.Mixed signal SoC tapeouts involving multiple instances of analog IPs.Low power / leakage management methodology and techniques.Extraction and characterization of IP elements.Education & ExperienceBS and 20 plus years of relevant industry experience (MSEE/PhD in Electrical Engineering Preferred)Additional Requirements25-30% Travel RequiredPay & BenefitsAt Apple, base pay is one part of our total compensation package and is determined within a range
This provides the opportunity to progress as you grow and develop within a role
The base pay range for this role is between $165,500 and $293,800, and your base pay will depend on your skills, qualifications, experience, and location.Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs
Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan
You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition
Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation
Learn more about Apple Benefits.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.Apple is an equal opportunity employer that is committed to inclusion and diversity
We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics
Learn more about your EEO rights as an applicant.
