Principal Digital Engineer at OSI Engineering

Our team is on the lookout for a talented Principal Digital Engineer to join our Memory Interface Chips team in Agoura Hills, California. You will work alongside some of the industry's brightest minds to develop cutting-edge products that enhance data speed and security.

Key Responsibilities:

• Planning: Lead digital design initiatives, manage projects, specify design blocks, conduct system-level simulations, and document processes.
• Implementation: Perform RTL design in Verilog, conduct linting and clock domain crossing (CDC) analysis, handle top-level integration, synthesis, timing analysis, and DFT-related tasks.
• Verification: Collaborate with the verification team on planning and execution, conduct simulations, debug block and system-level issues, perform formal verification, and prepare documentation for technical reviews and products/blocks.
• Flow and Methodology: Engage in a dynamic R&D environment to influence and develop methodologies that enhance technical direction.
• Collaboration: Interact with technical leaders and senior staff across engineering, marketing, and corporate development to drive successful technology and product development.

Qualifications:

• Experience and in-depth knowledge of Advantest V93k required 
• Bachelor’s or Master’s Degree in Electrical or Computer Engineering.
• 7+ years of relevant experience in digital, ASIC, or IC design.
• Proficiency in RTL coding with Verilog and/or VHDL.
• Extensive experience with standard ASIC software tools (synthesis, simulation, equivalence checking, static timing analysis).
• Strong scripting skills and familiarity with Linux/Unix environments, as well as basic C/C++ programming.
• Comprehensive understanding of the ASIC design flow.
• Proven success in digital leadership roles.
• Strong design and systems knowledge.
• Experience in design for verification (e.g., assertion-based strategies, code coverage, test plans) is a plus.
• Self-starter with excellent interpersonal skills and a proven ability to drive technical solutions across various disciplines.
• Additional knowledge of analog blocks, behavior modeling, DDR protocols, memory controllers, PCIe digital controllers, or embedded MCU subsystems is advantageous.

Salary Range: $116,700.00 to $200,000.00 (DOE)

Location:  Agoura Hills, California

Type: Full-time