RTL Analysis Methodology Engineer at Yoh
Mountain View, CA 94040
About the Job
*RTL Analysis Methodology Engineer*
Looking for an RTL Analysis Methodology Engineer to join an AI core design & verification team. This team is focused on architecting, developing, & verifying a new AI core. This new core is architected to support modern AI workloads for both inference & training use cases. The general purpose architecture is also used in many high performance computing apps. The person will need to have strong experience in RTL design, EDA tools, git & CI enablement.
*Scope:*
*RTL Methodology Development:* Design & implement scalable RTL analysis methodologies, covering areas such as linting, CDC [Clock Domain Crossing], RDC [Reset Domain Crossing],& power analysis.
*Tool Integration and Automation:* Integrate EDA tools & scripts for automation of RTL analysis workflows, ensuring repeatability & consistency across design projects. Set up/maintain flow regressions & QA.
*RTL Analysis:* Conduct analysis of RTL code to optimize design metrics, including area, timing, power, & clocking structures.
*Collaboration:* Work closely with RTL design & emulation teams to define/implement best practices, identifying areas for improvement in the RTL design flow.
*Required:*
Degree in Electrical Engineering, Computer Engineering, or equivalent hands-on experience.
4-5+ years of demonstrated experience with ASIC design, tools & methodologies.
Strong hands-on experience with RTL linting EDA tools.
Solid with HW description languages Verilog, SystemVerilog, etc.
Scripting experience in languages such as Tcl & Python.
Solid debug & problem-solving abilities, including experience working with EDA vendors to troubleshoot/resolve issues.
Solid comm skills.
*Pluses:*
Experience with synthesis, pre-silicon power estimation flow, Logical Equivalence Checking (LEC).
Experience with encryption & obfuscation of RTL for IP delivery to customers.
Emulator experience
*Estimated Min Rate*: $70.00
*Estimated Max Rate*: $95.00
Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.
Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Visit *[https://www.yoh.com/applicants-with-disabilities ](https://www.yoh.com/applicants-with-disabilities)
*to contact us if you are an individual with a disability and require accommodation in the application process.
For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.
Looking for an RTL Analysis Methodology Engineer to join an AI core design & verification team. This team is focused on architecting, developing, & verifying a new AI core. This new core is architected to support modern AI workloads for both inference & training use cases. The general purpose architecture is also used in many high performance computing apps. The person will need to have strong experience in RTL design, EDA tools, git & CI enablement.
*Scope:*
*RTL Methodology Development:* Design & implement scalable RTL analysis methodologies, covering areas such as linting, CDC [Clock Domain Crossing], RDC [Reset Domain Crossing],& power analysis.
*Tool Integration and Automation:* Integrate EDA tools & scripts for automation of RTL analysis workflows, ensuring repeatability & consistency across design projects. Set up/maintain flow regressions & QA.
*RTL Analysis:* Conduct analysis of RTL code to optimize design metrics, including area, timing, power, & clocking structures.
*Collaboration:* Work closely with RTL design & emulation teams to define/implement best practices, identifying areas for improvement in the RTL design flow.
*Required:*
Degree in Electrical Engineering, Computer Engineering, or equivalent hands-on experience.
4-5+ years of demonstrated experience with ASIC design, tools & methodologies.
Strong hands-on experience with RTL linting EDA tools.
Solid with HW description languages Verilog, SystemVerilog, etc.
Scripting experience in languages such as Tcl & Python.
Solid debug & problem-solving abilities, including experience working with EDA vendors to troubleshoot/resolve issues.
Solid comm skills.
*Pluses:*
Experience with synthesis, pre-silicon power estimation flow, Logical Equivalence Checking (LEC).
Experience with encryption & obfuscation of RTL for IP delivery to customers.
Emulator experience
*Estimated Min Rate*: $70.00
*Estimated Max Rate*: $95.00
Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.
Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Visit *[https://www.yoh.com/applicants-with-disabilities ](https://www.yoh.com/applicants-with-disabilities)
*to contact us if you are an individual with a disability and require accommodation in the application process.
For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.
