Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer - Capgemini
San Francisco, CA
About the Job
Physical Design Engineer
Job Description:
The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release to wafer fabrication using the latest Synopsys tools. The candidate should have a high aptitude for floor-planning the design of complex digital top level and/or blocks, with experience across the complete ASIC/SOC design flow including routing, static timing closure, EM/IR analysis and chip finishing.
Job Responsibility:
•Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation.
•Expertise in timing closure (STA) of high frequency blocks
•Handling blocks of high instance counts and complex designs – 1M instances and clock frequencies about 1 GHz
•Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
•Experience in Block-level and Full-chip integration.
•Knowledge of signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
•Understanding constraints and fixing design/timing techniques
•Block level implementation from netlist to GDS
•Understanding SI prevention, fixing methodology and implementation
•Proficient in layout edit techniques
•Proficient in Synopsys Fusion Compiler, ICC/ICC2, PTSi, and Cadence EDA Tool Suite
•Experience in Design Automation and UNIX system.
•Experience in Tcl/Tk, PERL, Python is a plus.
Desired Skills & Experience:
•Must possess 8 years of hands-on experience in handling block/chip level implementation from Netlist to GDSII
•Must possess hands on experience in timing closure and physical verification closure
•Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
•Experience in handling lower tech nodes that include 3nm, 5nm, 7nm, 10nm, 16nm, etc.
•Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such ICC/ICC2, Fusion Compiler or Cadence APR tools.
•Must have the ability to think on the spot for quick solutions and work-around at the time of tape-out to hit the schedule on time
•Must possess excellent scripting skills – TCL or Perl or Python
•Experience in Synthesis and Formal is a plus
•Excellent verbal and written communication skills are required.
•Must possess excellent debug skills, analytical skills, and the ability to work independently.
•Must be highly motivated and possess excellent team spirit
Synopsys Or Cadence EDA Tool Suite, STA, PrimeTime-Si, PNR, Python/TCL
Life at Capgemini
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:
+ Flexible work
+ Healthcare including dental, vision, mental health, and well-being programs
+ Financial well-being programs such as 401(k) and Employee Share Ownership Plan
+ Paid time off and paid holidays
+ Paid parental leave
+ Family building benefits like adoption assistance, surrogacy, and cryopreservation
+ Social well-being benefits like subsidized back-up child/elder care and tutoring
+ Mentoring, coaching and learning programs
+ Employee Resource Groups
+ Disaster Relief
About Capgemini Engineering
World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet.
Capgemini Engineering is an integral part of the Capgemini Group, a global leader in partnering with companies to transform and manage their business by harnessing the power of technology. The Group is guided every day by its purpose of unleashing human energy through technology for an inclusive and sustainable future. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2023 global revenues of €22.5 billion.
Get the Future You Want | www.capgemini.com
Disclaimer
Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.
Capgemini is committed to providing reasonable accommodations during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.
Click the following link for more information on your rights as an Applicant http://www.capgemini.com/resources/equal-employment-opportunity-is-the-law
Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.
Applicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini.
Job: _Developer_
Organization: _ERD PPL US_
Title: _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_
Location: _CA-San Francisco_
Requisition ID: _077101_
Job Description:
The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release to wafer fabrication using the latest Synopsys tools. The candidate should have a high aptitude for floor-planning the design of complex digital top level and/or blocks, with experience across the complete ASIC/SOC design flow including routing, static timing closure, EM/IR analysis and chip finishing.
Job Responsibility:
•Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation.
•Expertise in timing closure (STA) of high frequency blocks
•Handling blocks of high instance counts and complex designs – 1M instances and clock frequencies about 1 GHz
•Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
•Experience in Block-level and Full-chip integration.
•Knowledge of signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
•Understanding constraints and fixing design/timing techniques
•Block level implementation from netlist to GDS
•Understanding SI prevention, fixing methodology and implementation
•Proficient in layout edit techniques
•Proficient in Synopsys Fusion Compiler, ICC/ICC2, PTSi, and Cadence EDA Tool Suite
•Experience in Design Automation and UNIX system.
•Experience in Tcl/Tk, PERL, Python is a plus.
Desired Skills & Experience:
•Must possess 8 years of hands-on experience in handling block/chip level implementation from Netlist to GDSII
•Must possess hands on experience in timing closure and physical verification closure
•Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
•Experience in handling lower tech nodes that include 3nm, 5nm, 7nm, 10nm, 16nm, etc.
•Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such ICC/ICC2, Fusion Compiler or Cadence APR tools.
•Must have the ability to think on the spot for quick solutions and work-around at the time of tape-out to hit the schedule on time
•Must possess excellent scripting skills – TCL or Perl or Python
•Experience in Synthesis and Formal is a plus
•Excellent verbal and written communication skills are required.
•Must possess excellent debug skills, analytical skills, and the ability to work independently.
•Must be highly motivated and possess excellent team spirit
Synopsys Or Cadence EDA Tool Suite, STA, PrimeTime-Si, PNR, Python/TCL
Life at Capgemini
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:
+ Flexible work
+ Healthcare including dental, vision, mental health, and well-being programs
+ Financial well-being programs such as 401(k) and Employee Share Ownership Plan
+ Paid time off and paid holidays
+ Paid parental leave
+ Family building benefits like adoption assistance, surrogacy, and cryopreservation
+ Social well-being benefits like subsidized back-up child/elder care and tutoring
+ Mentoring, coaching and learning programs
+ Employee Resource Groups
+ Disaster Relief
About Capgemini Engineering
World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet.
Capgemini Engineering is an integral part of the Capgemini Group, a global leader in partnering with companies to transform and manage their business by harnessing the power of technology. The Group is guided every day by its purpose of unleashing human energy through technology for an inclusive and sustainable future. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2023 global revenues of €22.5 billion.
Get the Future You Want | www.capgemini.com
Disclaimer
Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.
Capgemini is committed to providing reasonable accommodations during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.
Click the following link for more information on your rights as an Applicant http://www.capgemini.com/resources/equal-employment-opportunity-is-the-law
Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.
Applicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini.
Job: _Developer_
Organization: _ERD PPL US_
Title: _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_
Location: _CA-San Francisco_
Requisition ID: _077101_
Source : Capgemini
