Silicon DD Engineer III - Pinnacle

IP RTL coding within the past 2-3 years is very important

Job Description:

• Silicon DD Engineer

Role Mandate:

• The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on architecture development and perform RTL coding on the next version of client’s IP.
• This candidate will have the opportunity to work on block design implementation for an IP that is going into future AR products.

Candidate Value Proposition:

• The ideal candidate will collaborate with a team of designers to work on graphics IP development.

Role Responsibilities (including, but not limited to):

• Own ASIC IP RTL implementation for IP blocks.
• Ensure RTL written meets quality checks like Lint/CDC/RDC.
• Collaborate closely with design team members, technical leads and the architecture team to ensure the block meets the power and performance requirements.
• Collaborate closely with the verification team to develop test plans and review test coverage.
• Perform IP integration
• Supervise the RTLtoGDS flow and assist with synthesis and timing closure
• Work with FPGA engineers to perform early prototyping
• Support handoff and integration of blocks into larger SOC environments
• Assist with Algorithm analysis.

Performance Measurement:

• Performance is measured based on meeting deadlines by delivering on time while meeting code quality metrics and DV quality metrics.

Must Have Skills:

• 4 plus years of experience as a Digital Design Engineer.
• Recent experience with IP RTL coding within the past 2 to 3 years, specifically for ASIC (Per CWAM, anything beyond would be a challenge)
• Experience having worked on a design from scratch – code from the ground up (outline / provide project work, if available)
• Experience in RTL coding and coding for low power in ASICs
• Experience in digital design µArchitecture
• Strong experience with Verilog and SystemVerilog coding
• Perl, TCL and Python (or similar) scripting experience

Nice to Have Skills:

• MSEE/CS or equivalent experience
• Experience developing IP for Graphics Processing Unit (GPU), CPU, Compression, or Video ASICs – experience working on coding for these industries (typically aligns with what this team is doing)
• Recent track record of projects where individual coded from ground up that were successfully taped out.
• Former client experience

Soft Skills:

• Strong verbal and written communication skills

Educational Requirements:

• BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience

Additional Note to the Recruiter – Do Not Distribute:

• The team is looking for engineers to do the actual design, not maintenance.
• Recent experience with RTL coding within the past 2 to 3 years (anything beyond would be a struggle).
• What are the top nonnegotiable skill sets required for this role?
• Experience in RTL coding, synthesis and/or SoC Integration.
• Experience in digital design µArchitecture.
• Familiarity with Verilog, system Verilog coding.
• Former AMD, NVIDIA, Apple, Qualcomm, Intel, Microsoft (on Silicon side) candidates (nicetohave).

Red Flags / Disqualifiers:

• Lack of RTL coding
• Lots of job hopping / large unexplained gaps within resume.
• Lighter side of industry experience
• Lots of shortterm engagements

CWAM will reject candidates based on resume if:

• Lack of hands-on coping / IP block design and / or no recent design experience (recent within 2 to 3 years).
• Very rusty on RTL coding, most design work was 10 or so years back.
• Candidate also lacked experience in low power design.
• Basic coding issues in the design portion of the interview
• Candidate's design experience seemed to be limited to mostly FSM based designs (i.e. no caches, some limited fixed point math in filters).
• Candidate struggled a lot with two fairly basic coding questions.
• Experience seems to be RF related, not IP block design
• Looks like very limited RTL design experience mostly around DDR PHY design, not relevant to client’s designs
• No ASIC RTL design experience.
• Only design seems to be as a FW engineer targeting FPGA.
• GPU experience seems to be system verification/test infrastructure related, not design
• Limited block design experience, seems mostly integration related.
• Design experience seems to be very simple blocks like performance monitors.
• Experience is DV and silicon validation, not design.

Pay Range: $85++/ hr

The specific compensation for this position will be determined by a number of factors, including the scope, complexity and location of the role as well as the cost of labor in the market; the skills, education, training, credentials and experience of the candidate; and other conditions of employment. Our fulltime consultants have access to benefits including medical, dental, vision and 401K contributions as well as any other PTO, sick leave, and other benefits mandated by appliable state or localities where you reside or work.

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