SoC Design Engineer at Omnivision Technologies
Santa Clara, CA 95050
About the Job
DescriptionJob Duties: Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation; Work closely with back-end team in floor-planning, timing closure and DFT; Conduct image sensor array/analog related timing control design and STA; Perform chip bring-up, validation and debugging; Design, integrate and validate ISP data pipes according to PRD/design specification and system architecture of SoC CIS products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc.; Additionally, work on enhancing the functionality of the grp_holdip
Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS; Work with sensor digital and analog engineers for system design, integration and validation; Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation; Work with algorithm and application engineers for image tuning and qualification; Conduct silicon validation, debugging and tuning.Requirements: A Master’s degree in Electrical Engineering, Computer Engineering, or a related field.Must possess the following skills:ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog programming languages.RTL development: Verilog, Synthesis, Timing Analysis, Lint, CDC and RDC.VLSI system: high performance and low power design techniques, physical design, scripting in Python.Digital System Design: ASIC design, FPGAs, test benches, simulation, synthesis, timing analysis, post-synthesis simulation, FIFOs, handshaking, memory interface, PCI bus protocol, CAD tools, coding in Verilog and VHDL, proficient in using Vivado tool.Annual base salary for this role in California, US is expected to be between $151,091 - $155,000
Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS; Work with sensor digital and analog engineers for system design, integration and validation; Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation; Work with algorithm and application engineers for image tuning and qualification; Conduct silicon validation, debugging and tuning.Requirements: A Master’s degree in Electrical Engineering, Computer Engineering, or a related field.Must possess the following skills:ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog programming languages.RTL development: Verilog, Synthesis, Timing Analysis, Lint, CDC and RDC.VLSI system: high performance and low power design techniques, physical design, scripting in Python.Digital System Design: ASIC design, FPGAs, test benches, simulation, synthesis, timing analysis, post-synthesis simulation, FIFOs, handshaking, memory interface, PCI bus protocol, CAD tools, coding in Verilog and VHDL, proficient in using Vivado tool.Annual base salary for this role in California, US is expected to be between $151,091 - $155,000
Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
