SoC UPF Design Engineer, Google Cloud - Google
Sunnyvale, CA
About the Job
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with RTL coding using Verilog/SystemVerilog.
- 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with low-power design techniques such as clock gating, power gating, and DVFS.
- Experience with SOC implementation standards, interfaces (i.e. AXI) and scripting languages (i.e. Tcl, Python or Perl).
- Experience in UPF for low-power design, including power intent specification, verification, and implementation.
- Experience with formal verification methods and design for testability (DFT) techniques.
- Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
You will join a team working on SoC-level RTL design for our datacenter accelerators. In this role you will own top-level RTL, architecture, design and implementation of global communication busses, and integration of complex ASIC designs. This is a cross-functional and central role that will require interactions with numerous ASIC development teams. You will own deliverables to the cross-functional teams (i.e. Physical Design, Verification, Validation, Firmware) at various project milestones. You will also be involved in defining and creating methodologies that enable a highly efficient design environment for all ASIC engineers.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Contribute to the development and successful delivery of complex silicon systems. Design and implement RTL code for various digital blocks, including complex control logic, and on-chip data paths.
- Develop and maintain Unified Power Format (UPF) specifications for power management of the design, including power domain definitions, power state transitions, and isolation strategies.
- Take ownership of power signoff using industry standard tools coordinating deliverables from block owners.
- Collaborate with verification and physical design engineers to ensure the functionality and power integrity of the design.
- Contribute to the development and improvement of design flows, tools and methodologies.
Source : Google
