Sr Engineer Device Engineering at GlobalFoundries U.S. 2 LLC
Essex Junction, VT
About the Job
Title: Sr Engineer Device Engineering
Job duties:
Develop ESD and Latch up protection device/circuit solutions for differentiated technology portfolio. Design test macros for electrical characterization and JEDEC qualification. Define test plans and execute qualification plans per industry standards. Analyze electrical test data, develop ESD/ Latch-up-related physical ground rules and develop supporting documentation, such as user guides and application notes. Submit and track failure analysis samples to understand observed failure and defect modes. Ensure correct process monitors are in place for robust ESD/Latch-up manufacturing. Collaborate closely with Quality, Reliability, and Technology teams for technology qualification. Work with circuit IO Design Teams to cooptimize I/O and ESD performance.
Requirements: Master’s degree, or foreign equivalent, in Electrical Engineering or closely related field of study plus 2 years of post-baccalaureate experience in the job offered, as an Engineer, or a similar occupation. Must have 2 years of experience in: (1) silicon process technology development and semiconductor device design; (2) Electronic Design Automation [EDA] tools; (3) Design of experiments for process/technology definition and optimization; (4) Data analysis tools (JMP) and data mining; (5) implementing CIPs for critical parameters; (6) Manufacturing systems for lot processing and disposition (SiView, Experiment Management System); (7) Semiconductor process fabrication flow. Less than 10% travel required, domestic/international. Salary Range: $105,477 – $115,500. Apply online at www.gf.com/careers/ #JR-2403965.
Job duties:
Develop ESD and Latch up protection device/circuit solutions for differentiated technology portfolio. Design test macros for electrical characterization and JEDEC qualification. Define test plans and execute qualification plans per industry standards. Analyze electrical test data, develop ESD/ Latch-up-related physical ground rules and develop supporting documentation, such as user guides and application notes. Submit and track failure analysis samples to understand observed failure and defect modes. Ensure correct process monitors are in place for robust ESD/Latch-up manufacturing. Collaborate closely with Quality, Reliability, and Technology teams for technology qualification. Work with circuit IO Design Teams to cooptimize I/O and ESD performance.
Requirements: Master’s degree, or foreign equivalent, in Electrical Engineering or closely related field of study plus 2 years of post-baccalaureate experience in the job offered, as an Engineer, or a similar occupation. Must have 2 years of experience in: (1) silicon process technology development and semiconductor device design; (2) Electronic Design Automation [EDA] tools; (3) Design of experiments for process/technology definition and optimization; (4) Data analysis tools (JMP) and data mining; (5) implementing CIPs for critical parameters; (6) Manufacturing systems for lot processing and disposition (SiView, Experiment Management System); (7) Semiconductor process fabrication flow. Less than 10% travel required, domestic/international. Salary Range: $105,477 – $115,500. Apply online at www.gf.com/careers/ #JR-2403965.
