Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX
Irvine, CA 92602
About the Job
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.SR
SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system
Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide
We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together
We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation)
In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe
These chips are enabling connectivity in places it has previously not been available, affordable or reliable
Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Perform partition synthesis and physical implementation steps (e.g
synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)Develop/improve physical design methodologies and automation scripts for various implementation stepsClosely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffsResolve design/timing/congestion and flow issues, identify potential solutions and drive executionRun, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage dropBASIC QUALIFICATIONS:Bachelor’s degree in electrical engineering, computer engineering or computer science5+ years of ASIC and/or physical design flow development experience in industryPREFERRED SKILLS AND EXPERIENCE:Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flowsStrong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithmsKnowledge of deep sub-micron FinFET and CMOS solid state physicsKnowledge of CMOS digital design principles, basic standard cells their functionality, standard cell librariesUnderstanding of CMOS power dissipation in deep submicron processes leakage/dynamicFamiliar with CMOS analog circuit and physical designKnowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flowsGood scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environmentADDITIONAL REQUIREMENTS: Must be willing to work extended hours and weekends as needed COMPENSATION AND BENEFITS:Pay range: Physical Design Engineer/Senior: $160,000.00 - $220,000.00/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.Base salary is just one part of your total rewards package at SpaceX
You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan
You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks
You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year
Exempt employees are eligible for 5 days of sick leave per year.ITAR REQUIREMENTS:To conform to U.S
Government export regulations, applicant must be a (i) U.S
citizen or national, (ii) U.S
lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C
§ 1157, or (iv) Asylee under 8 U.S.C
§ 1158, or be eligible to obtain the required authorizations from the U.S
Department of State
Learn more about the ITAR here
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.SR
SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system
Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide
We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together
We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation)
In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe
These chips are enabling connectivity in places it has previously not been available, affordable or reliable
Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Perform partition synthesis and physical implementation steps (e.g
synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)Develop/improve physical design methodologies and automation scripts for various implementation stepsClosely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffsResolve design/timing/congestion and flow issues, identify potential solutions and drive executionRun, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage dropBASIC QUALIFICATIONS:Bachelor’s degree in electrical engineering, computer engineering or computer science5+ years of ASIC and/or physical design flow development experience in industryPREFERRED SKILLS AND EXPERIENCE:Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flowsStrong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithmsKnowledge of deep sub-micron FinFET and CMOS solid state physicsKnowledge of CMOS digital design principles, basic standard cells their functionality, standard cell librariesUnderstanding of CMOS power dissipation in deep submicron processes leakage/dynamicFamiliar with CMOS analog circuit and physical designKnowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flowsGood scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environmentADDITIONAL REQUIREMENTS: Must be willing to work extended hours and weekends as needed COMPENSATION AND BENEFITS:Pay range: Physical Design Engineer/Senior: $160,000.00 - $220,000.00/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.Base salary is just one part of your total rewards package at SpaceX
You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan
You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks
You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year
Exempt employees are eligible for 5 days of sick leave per year.ITAR REQUIREMENTS:To conform to U.S
Government export regulations, applicant must be a (i) U.S
citizen or national, (ii) U.S
lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C
§ 1157, or (iv) Asylee under 8 U.S.C
§ 1158, or be eligible to obtain the required authorizations from the U.S
Department of State
Learn more about the ITAR here
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at
(310) 363-6000
. 