System Architect, AMS Engineering at Celestial AI
Santa Clara, CA 95050
About the Job
About Celestial AIWith the growth in Generative AI, data center infrastructure it is not just about the System on Chip but about the System of Chips
In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity
Celestial AI's Photonic Fabric is the next-generation interconnect technology offering a10X increase in performance and energy efficiency over competitive technologies.The Photonic Fabric is available to our customers in multiple technology offerings, including optical chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB)
This enables our customers to seamlessly integrate high bandwidth, low power, low latency optical interfaces into their AI accelerators and GPUs
The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging flows
This ease of integration enables XPUs to have optical interconnects for compute-to-compute and compute-to-memory fabrics that deliver tens of Tbps bandwidth with nano-second latencies.This innovation empowers hyperscalers to improve the efficiency and economics of AI processing by optimizing the XPUs needed for training and inference and significantly lowering the TCO2 impact
To support customer engagements, Celestial AI is cultivating a Photonic Fabric ecosystem
These tier-1 partnerships consist of custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.Job Description:In this role you will drive the innovative System Architecture for high-speed analog Serdes (low-power, high-performance AMS solutions customized for AI application).ESSENTIAL DUTIES AND RESPONSIBILITIES:Understanding digital signal processing and digital communications for optical interfacesModelling/simulation/analysis of systems including high speed analog components (ADC, DAC, drivers, TIA), opto-electronic components (optical modulators, optical mixers, photodiodes, lasers, optical mux/demux, optical amplifiers), fiber impairments (CD, PMD, non-linearities) and DSP algorithms (calibration of analog and optical nonidealities, equalizers, carrier frequency/phase recovery, timing recovery)Analysis and modelling of systems to drive definition of standards in OIF/IEEE/ITU-TWork with lab equipment (spectrum analyzers, scopes, VOA, lasers, ASE generators etc.)Design experiments to collect/analyze data to enable definition of next generation DSPDebug complex optical, analog and signal processing problemsDesign and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for both analog and digital designersCreate DSP and FEC hardware block specifications appropriate for RTL implementationPerform research activities in digital signal processing for SerDes and optical channelsWork with designers to ensure circuit architecture can be efficiently implementedDevelop/perform behavioral modeling of mixed-signal circuit designs for transceiversProvide guidance on test plans for lab characterization once design comes back from fabParticipate in chip lab bring upShould be comfortable working with lab equipmentQUALIFICATIONS:Requires master’s degree with 6+ years of experience in related areas of expertise or PhD with 3+ years of experienceKnowledgeable about the common high-speed serial data protocols NRZ/PAM4 and system standardsStrong experience in communication system modeling in Matlab, C and/or PythonExperience in high-speed DSP, especially FFE/DFE, Clock and Data Recovery (CDR)Experience with FEC (RS, soft decoding, Viterbi algorithm)Experience with high-speed Analog Serdes and the associated calibration algorithmsExperience with debugging complex analog issues to improve system performance is requiredKnowledge of digital design of DSP blocks will be a huge plusLocation: This role can be based out of Santa Clara, CA, Orange County, CA or Toronto, Ontario, CanadaFor California location:As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity
The target base salary for this role is approximately $175,000.00 - $225,000.00
The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.Celestial AI Inc
is proud to be an equal opportunity workplace and is an affirmative action employer.#LI-Onsite
In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity
Celestial AI's Photonic Fabric is the next-generation interconnect technology offering a10X increase in performance and energy efficiency over competitive technologies.The Photonic Fabric is available to our customers in multiple technology offerings, including optical chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB)
This enables our customers to seamlessly integrate high bandwidth, low power, low latency optical interfaces into their AI accelerators and GPUs
The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging flows
This ease of integration enables XPUs to have optical interconnects for compute-to-compute and compute-to-memory fabrics that deliver tens of Tbps bandwidth with nano-second latencies.This innovation empowers hyperscalers to improve the efficiency and economics of AI processing by optimizing the XPUs needed for training and inference and significantly lowering the TCO2 impact
To support customer engagements, Celestial AI is cultivating a Photonic Fabric ecosystem
These tier-1 partnerships consist of custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.Job Description:In this role you will drive the innovative System Architecture for high-speed analog Serdes (low-power, high-performance AMS solutions customized for AI application).ESSENTIAL DUTIES AND RESPONSIBILITIES:Understanding digital signal processing and digital communications for optical interfacesModelling/simulation/analysis of systems including high speed analog components (ADC, DAC, drivers, TIA), opto-electronic components (optical modulators, optical mixers, photodiodes, lasers, optical mux/demux, optical amplifiers), fiber impairments (CD, PMD, non-linearities) and DSP algorithms (calibration of analog and optical nonidealities, equalizers, carrier frequency/phase recovery, timing recovery)Analysis and modelling of systems to drive definition of standards in OIF/IEEE/ITU-TWork with lab equipment (spectrum analyzers, scopes, VOA, lasers, ASE generators etc.)Design experiments to collect/analyze data to enable definition of next generation DSPDebug complex optical, analog and signal processing problemsDesign and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for both analog and digital designersCreate DSP and FEC hardware block specifications appropriate for RTL implementationPerform research activities in digital signal processing for SerDes and optical channelsWork with designers to ensure circuit architecture can be efficiently implementedDevelop/perform behavioral modeling of mixed-signal circuit designs for transceiversProvide guidance on test plans for lab characterization once design comes back from fabParticipate in chip lab bring upShould be comfortable working with lab equipmentQUALIFICATIONS:Requires master’s degree with 6+ years of experience in related areas of expertise or PhD with 3+ years of experienceKnowledgeable about the common high-speed serial data protocols NRZ/PAM4 and system standardsStrong experience in communication system modeling in Matlab, C and/or PythonExperience in high-speed DSP, especially FFE/DFE, Clock and Data Recovery (CDR)Experience with FEC (RS, soft decoding, Viterbi algorithm)Experience with high-speed Analog Serdes and the associated calibration algorithmsExperience with debugging complex analog issues to improve system performance is requiredKnowledge of digital design of DSP blocks will be a huge plusLocation: This role can be based out of Santa Clara, CA, Orange County, CA or Toronto, Ontario, CanadaFor California location:As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity
The target base salary for this role is approximately $175,000.00 - $225,000.00
The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.Celestial AI Inc
is proud to be an equal opportunity workplace and is an affirmative action employer.#LI-Onsite
